The subject of this application relates generally to the field of integrated circuit (IC) design and, more particularly, to reducing critical path schematics apparatus and methods.
Critical path analysis is one of the most important stages of circuit design, in part, because it can help determine the speed at which a circuit may be run. As circuits are quickly becoming more complicated, critical path analysis, as with many other circuit analysis techniques, is becoming increasingly computerized for efficiency purposes.
Also, as circuits grow in complexity (sometimes reaching thousands and sometimes millions of gates), it is imperative to decrease the number of computer resources and hours spent on evaluating these designs. This is extremely important with respect to critical path analysis. Especially, in the current climate of competition, it is imperative that the speed of a circuit be determined before investing substantial amounts of money on making and marketing a device that may be dwarfed by solutions from competitors.
Accordingly, critical path analysis is not only a tool for engineers to determine if their circuit design works, but also a tool for a marketing and finance division of a company to determine whether a given circuit design is worthy of pursuing.
Generally, circuit designers use a software program, such as HSpice provided by Avant Corporation of Fremont, Calif., to simulate the critical path schematics for their designs. Since the logic gates have different delays through them for rising and falling output nodes, the critical path of a circuit would have to be simulated for both rising and falling edges of a final output node. This requires creating at least two different schematics and simulations to calculate these delays.
After running these simulations, the higher of the rising or falling delays represents the worst-case delay. And, the worst-case delay in turn defines the final delay of the circuit. The final delay indicates the maximum frequency at which a design may safely run. Accordingly, it is important to set up these simulations carefully and efficiently.
The present invention, which may be used/set up on a general-purpose digital computer, includes methods and apparatus to provide efficient critical path analysis of a design, utilizing single or multiple processors.
In an embodiment, the techniques described herein disclose two devices that can be used to simulate both rising and falling delays through gates in a critical path using only one schematic and, hence, one simulation.
In another embodiment, an apparatus disclosed may assist in creating a single critical path schematic which can be used to simulate both rising and falling edge delays. This saves time as only one schematic and, hence, one simulation is required instead of the two generally required.
In yet a different embodiment, a method of efficiently performing critical path analysis is disclosed. The method includes providing a device to assist in determining both rising and falling delays for the critical path analysis of a gate; coupling an input of the device to a controlling input of the gate; coupling an output of the device to a non-controlling input of the gate, the device having an I/O characteristic wherein: signals at both the input and output of the device rise and fall substantially simultaneously on a first edge; and on a remaining edge, a signal at the device output follows one of a rise and a fall of a signal at the device input after a output node delay; and determining the rising and falling delays for the critical path analysis of the gate utilizing the device.